1. Field of the Invention
This invention relates to a semiconductor integrated circuit, specifically to a semiconductor integrated circuit that is reduced in a noise level.
2. Description of the Related Art
Higher speed and higher integration of a digital circuit have been realized as semiconductor manufacturing processes proceed to finer geometries. As a result, reducing a die size, reducing a cost per function due to the increased integration, and integrating a large scale system into a single chip are made possible. On the other hand, an analog circuit needs to be formed using transistors having certain dimensions of a gate width and a gate length in order to keep required signal quality even when the manufacturing processes have attained the finer geometries.
Also, the analog circuit is prone to reduction in a dynamic range and limitation on choices of circuit topologies due to a reduced power supply voltage associated with the finer geometries. Nevertheless, increasing performance of the analog circuit is essential in developing an analog-digital mixed LSI.
FIG. 8 is a circuit diagram of an operational amplifier that is an example of the analog circuit. The operational amplifier is of a P-channel type MOS transistor input type and is structured to have a single-ended output. P-channel type MOS transistors M61, M62 and M65 and N-channel type MOS transistors M63 and M64 constitute a first stage differential amplifier circuit 11. Each of differential input voltages VINN and VINP is applied to a gate of corresponding each of the transistors M61 and M62 that serve as differential input transistors. A P-channel type MOS transistor M66 and an N-channel type MOS transistor M67 constitute a second stage amplifier circuit 12, and an output voltage VOUT is obtained from a connecting node between them.
A phase compensation circuit 3 composed of a resistor RZ for zero cancellation and a capacitor CC for phase compensation, which are connected with each other in series, is connected between the first stage differential amplifier circuit 11 and the second stage amplifier circuit 12 so that the operational amplifier is prevented from oscillation.
A bias circuit 4 is composed of P-channel type MOS transistors M51, M53, M55 and M57, N-channel type MOS transistors M52, M54, M56 and M58 and a resistor RB1. When a power down signal PWDB applied to a gate of the N-channel type MOS transistor M52 turns to an H level, the N-channel type MOS transistor M52 is turned on to put the bias circuit 4 into operation. Thus, a bias voltage required for operations of the operational amplifier is supplied to a gate of the P-channel type MOS transistor M65 that serves as a current source transistor of the first stage differential amplifier circuit 11 and a gate of the P-channel type MOS transistor M66 that serves as a load transistor of the second stage amplifier circuit 12. This kind of operational amplifier is disclosed in Japanese Patent Application Publication No. 2009-225083.
A signal level (a level of each of the differential input voltages VINN and VINP, for example) that is workable with the operational amplifier is reduced as a power supply voltage VDDH supplied to the operational amplifier is reduced. When the signal level is reduced, there is caused a reduction in SNR (Signal to Noise Ratio) that is one of essential characteristics of the analog circuit. It is necessary to reduce a noise level of the operational amplifier itself so that the performance of the operational amplifier is enhanced even when the signal level is reduced.
FIG. 9 shows noise characteristics of a MOS transistor. The noise of the MOS transistor is primarily made of flicker noise distributed in a low frequency band and thermal noise distributed over a broad band. The SNR can be improved by reducing the flicker noise and the thermal noise that approximately determine the noise of an overall circuit composed of the MOS transistors.
First, the flicker noise, that is one of noise sources of the MOS transistor, is explained.
Flicker noise power Vnf2 per unit band width is given by a following equation (1).Vnf2=K/(Cox×W×L)×(1/f)  (1)where K is a constant dependent on the manufacturing processes, Cox is a gate oxide film capacitance per unit area, W is a gate width of the MOS transistor, L is a gate length of the MOS transistor, and f is an operating frequency of the MOS transistor.
The flicker noise is characterized by that it increases as the frequency decreases and decreases as the frequency increases. Particularly in the frequency band dealing with voice signals and audio signals, the flicker noise often makes dominant noise and reducing it is essential. The flicker noise can be reduced by increasing a gate area of the MOS transistor because it is inversely proportional to the gate width and the gate length of the MOS transistor.
Next, the thermal noise, that is another of the noise sources of the MOS transistor, is explained. In the case where the input signal applied to the gate is amplified (most of the cases), the thermal noise Vnin2 per unit band width is given by a following equation (2).Vnin2=(8×k×T)/(3×gm)  (2)where k is Boltzmann's constant, T is temperature in Kelvin, and gm is transconductance of the MOS transistor. The transconductance gin of the MOS transistor is given by a following equation (3).gm=√{square root over ((2×μ×Cox×(W/L)×Id)}  (3)where μ is mobility of the MOS transistor, Cox is the gate oxide film capacitance per unit area, W is the gate width of the MOS transistor, L is the gate length of the MOS transistor, and Id is a drain current of the MOS transistor.
The thermal noise is uniformly distributed from low frequency to high frequency. Reducing a level of the thermal noise is essential since it makes dominant noise in signal dealing with relatively high frequency or in a discrete system (sampling data system). The thermal noise can be reduced by increasing the transconductance of the MOS transistor because it is inversely proportional to the transconductance.
Taking the operational amplifier shown in FIG. 8 as an example, it is generally known that the flicker noise occupies major portion of noise with the P-channel type MOS transistors M61 and M62 and the N-channel type MOS transistors M63 and M64 in the overall circuit. Although reducing the flicker noise requires increasing the gate area of each of the MOS transistors, simply increasing the gate area results in an increased die size. Also, increasing the sizes of the transistors affects adjacent parasitic capacitances and possibly increases current consumption.
Chopper modulation technique is known as a method to reduce the flicker noise without increasing the area of the transistor. The chopper modulation technique is a method to modulate low frequency noise to higher frequency side with a modulation clock. However, this method requires a clock generation circuit to generate the modulation clock, a switch control circuit, a switching circuit and the like, so that a size of the circuit is prone to increase. In addition, when it is applied to an integrated circuit composed of a plurality of circuits in which the flicker noise is dominant, each of the plurality of circuits requires the circuits described above, resulting in increased size of the circuit and increased current consumption.
Furthermore, when it is used in a continuous time system, a filter to remove a chopper clock signal is required in a subsequent stage.
Reducing the thermal noise requires increasing the transconductance of the MOS transistor. Taking the operational amplifier shown in FIG. 8 as an example, the P-channel type MOS transistors M61 and M62 are subject to the requirement. The transconductance is increased by increasing a W/L ratio, or by increasing a drain current.
However, the increase in the W/L ratio leads to an increase in the area, and the increase in the drain current leads to an increase in the current consumption. In addition, in the discrete time system (sampling data system), the thermal noise appears in a signal band as a folding noise to increase the noise in the signal band, since the thermal noise is distributed over the broad band. Although a sampling method using a sampling frequency higher than the required signal band is known to reduce the influence of the thermal noise due to the folding, it leads to an increase in the current consumption because the operating frequency is increased.
As the processes proceed to the finer geometries and the power supply voltage is reduced, the dynamic range is inevitably reduced to degrade analog characteristics. Under the circumstances described above, there is caused a problem that it is difficult to maintain or improve the characteristics of the semiconductor integrated circuit such as the operational amplifier without increasing the size (increasing the area) of the circuit or increasing the current consumption.